Faculty & Staff
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Mr. Divya Kiran
Assistant Professor
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School/College
Faculty of Engineering and Technology
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Department
Department of Electronics and Communication Engineering
Mr. Divya Kiran has been awarded M.Sc (Engg.) in VLSI System Design by Coventry University, UK in 2013 and B.E. in ECE by Anna University in 2010. He is currently pursuing Ph.D. in the domain of machine learning and computer vision. He has been part of IEEE as member and treasurer of RUAS Student Branch. His current research interests are Low power VLSI Architectures, Hardware Acceleration of Machine Learning Algorithms, Hardware Implementation of Computer Vision Applications, Physical Design optimization for VLSI, Hardware implementation of Natural Language Processing, Cybersecurity, Hardware security and Edge Computing Model Design. He has 9+ years of experience in teaching and research. He has published 4 national journal papers and 10 international conference papers.
Qualifications
- Ph.D. in Computer Vision
MS Ramaiah University of Applied Sciences, Pursuing
- M.Sc. in VLSI System Design
Coventry University, 2013
- B.E. in ECE
Anna University, 2010
Experience
Total Years of Experience9 Years 9 Months
Academic Experience
9 Years 9 Months
Training Experience (With Topics)
Corporate trainings for companies such as Robert Bosch and Altran on ECU performance, High Speed Board Design, ASIC Physical Design etc.
Low power VLSI Design, Hardware Acceleration of Machine Learning Algorithms, Hardware Security, Neuromorphic Computing, Edge Computing
International Conference Papers
- D. Kiran, A. I. Rasheed, and H. Ramasangu, "FPGA implementation of blob detection algorithm for object detection in visual navigation," in Circuits, Controls and Communications (CCUBE), 2013 International conference on, 2013, pp. 1-5.
- Patil, Swapnil, D. V. Manjunatha, and Divya Kiran. "Design of speed and power efficient multipliers using vedic mathematics with VLSI implementation." Advances in Electronics, Computers and Communications (ICAECC), 2014 International Conference on. IEEE, 2014.
- Akshay, A., Divya Kiran, P. Chandramohan, and Punithavathi Duraiswamy. "Design and analysis of Phase Locked Loop for low power wireless applications." In Emerging Devices and Smart Systems (ICEDSS), Conference on, pp. 61-65. IEEE, 2016.
- Arpitha .T, Divya Kiran, V.S.N. Sitaram Gupta, Punithavathi Duraiswamy, “FPGA-GSM based Gas Leakage Detection System” INDICON-2016, IEEE, 2016
- Prakruthi, U.S., Kiran, D. and Ramasangu, H., 2018, January. High performance neural network based acoustic scene classification. In 2018 2nd International Conference on Inventive Systems and Control (ICISC) (pp. 781-784). IEEE.
- Md. Shahmustafa, Divya Kiran, Hariharan Ramasangu, 2018 February, An Efficient CNN Architecture for Image Classification on FPGA Accelerator, IEEE, ICAECC, 2018
- Nida Ul Islam, Divya Kiran, Hariharan Ramasangu, System-on-Chip Implementation of Situational Awareness System for Autonomous Cars, IEEE, INDICON, 2018
- R Likhithashree, Divya Kiran, Design of Power-Efficient Ring Oscillator based Physically Unclonable Functions for FPGA, IEEE, ICEECCOT, 2019
- R Likhithashree, Divya Kiran, Area-Efficient Physically Unclonable Functions for FPGA using Ring Oscillator, IEEE, ICIMIA, 2020
National Journal Papers
- Divya Kiran, H. Ramasangu, “Improved Connected Component Algorithm Using Run-based Approach” RUAS-SASTech Journal, Vol. 15, 2016.
- N Nandana, Divya Kiran, Hariharan Ramasangu, 2017, FPGA Implementation of Efficient Convolution Architecture for CNN. In 2017 40th International Conference on Telecommunications and Signal Processing (TSP)
- Pagadala Gowri Lahari, Divya Kiran, 2018, BCD Approach Based High Performance Floating Point Multiplier for DSP Applications, RUAS-SASTech Journal, Vol 17, (pp. 9-12)
IEEE
Awarded
Punithavathi Duraiswamy, Divya Kiran and Naveen R “Method and Device for Generating a QPSK Signal”, Indian Patent Application : 6814/CHE/2015, December 21, 2015.
Applied
Divya Kiran, A. I. Rasheed, and H. Ramasangu “Method, System and Apparatus for Object Detection” Indian Patent Application : 3573 / CHE / 2014,
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