M. S. Ramaiah University of Applied Sciences
Private University Estd. in Karnataka State by Act No. 15 of 2013
(UGC Approved, NIRF-MHRD Ranked)
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Project Abstracts - 2015
M.Sc. Student Projects
VLSI System Design
Sl.No.
Project Title
1
Design of 2.4GHz Integer Phase Locked Loop
2
Implementation of Unsigned Multiplier using Efficient Carry- Select Adder for DSP Application
3
Design and Implementation of RSA Architecture using Modified Nikilam Multiplier
4
Design and Implementation of Improved Architecture for QPSK Modulator in FPGA
5
Design and Implementation of 3D-DWT Architecture for OFDM
6
Design and Analysis of Bandgap Voltage Reference in 32 nm FinFET Technology
7
Design and VLSI Implementation of DDR-MPLL with Non Integer Clock Divider and Duty Cycle Corrector in 22 nm CMOS Process Technology
M. S. Ramaiah University of Applied Sciences
